Beam intensity control for different writing rates in a display system

ABSTRACT

The invention comprises an arrangement for controlling the uniform intensity of different length displayed strokes, produced at different writing rates by a deflectable beam of a CRT, during a series of equal duration clock periods. The arrangement which is provided with the writing rates of each stroke along the X and Y axes of the display surface, estimates stroke length L; L is derived by implementing k(X/2 + Y/2 + P/2), where X and Y are the writing rates along the two axes, P is the greater of the two rates and k is either 1 or preferably 0.94. The estimated stroke length is used to control beam intensity as the beam is deflected from the stroke&#39;&#39;s start point to its end point.

United States Patent Koussa et al.

[54] BEAM INTENSITY CONTROL FOR DIFFERENT WRITING RATES IN A DISPLAYSYSTEM 12/1969 Bouchard ..3l5/22 9/1968 Bradley et al ..3l5/l8 R PrimaryExaminer-Benjamin R. Padgett [72] Inventors: Edward I' T. Koussa, YorbaLinda; Assistant potenza Fulhrwn, Attorney-James K. Haskell andWalter 1. Adam 0 a I [73] Assignee: Hughes Aircraft Company, Culver [57]ABSTRACT y. Calif- The invention comprises an arrangement for con- J 8,the uniform intensity Of different length dlS- played strokes, producedat difi'erent writing rates by a 1 PP -F 44,465 deflectable beam of aCRT, during a series of equal I duration clock periods. The arrangementwhich is pro- [52] U CL 3 2 A 315,18 vided with the writing rates ofeach stroke along the X [51] bk Cl oi, 29/70 d Y axes of the displaysurface, estimates stroke a: l g h L i d i d i pl i g [58] Field ofSearch ..315/22, 27 R, 18, 340/324 A P12) where x and Y are me writingrates along the two axes; P is the greater of the two rates and k is[56] References cited either i or preferably 0.94. The estimated strokeUNTED STATES PATENTS length is used to control beam intensity as thebeam is deflected from the strokes start point to its end point.3,537,098 10/1970 Nielsen ctval. ..3I5/18 R 3,394,367 7/1968 Dye.315]!!! R 19 Claims, 11 Drawing Figures 1 7732 ra 1m ZZ I I a If: v 4/4/) m I 4 ax Mr KAI/lid! was? 7 awr JIMWM any -0- 41:25:41, act 7 l a j52147: 4 2: 1 74 (I 3' j /fi/6/M) 2 4 l a/u44 /4z4A/z 5515,55

PATENTED on: 19 Ian I SHEU 2 0F, 5

m nnow 19 m2 SHEET Q UF 5 K 5km" PATENTEU I97? 3. 706, 906

sum 5 [IF 5 BEAM INTENSITY CONTROL FOR DIFFERENT WRITING RATES IN ADISPLAY SYSTEM The invention herein described was made in the course ofor under a Contract or Subcontract thereunder with the Air Force.

BACKGROUND OF THE INVENTION 1. Field of the Invention: v

The present invention generally relates to a digitallycontrolled displaysystem and, more particularly, to a novel beam intensity controlarrangement for such a display system.

2. Description of the Prior Art:

Typically, in a digitally-controlled display system of the type whichincludes a display unit, such as a cathode ray tube (CRT), each line orsymbol is displayed by deflecting the beam of the tube to successivepoints on the tubes display surface to form successive strokes. Theamplitudes and relationships of beam deflection voltages for each strokecontrol the stroke length and its direction along two orthogonal axes,which are generally referred to as the X and Y axes. Although eachstroke is produced during an equal time period, which is the clockperiod of the digital circuitry, since strokes lengths are notnecessarily equal, the displayed strokes are of varying intensitiesunless the beam's intensity is controlled as a function of each strokeslength.

In the prior art, beam intensity control is accomplished by generatingan analog signal which is proportional to the rates of change of thedeflection voltages which are used to deflect the beam to produce eachstroke. However, this can be accomplished only by employing voltagedifferentiating circuits. These circuits increase system complexity andoften do not provide sufficient control for the production of a displaywith a high enough intensity uniformity. Thus, a need exists for a newarrangement for beam intensity control for a display system in whichdifferent length strokes are formed or written during equal clockperiods.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of thepresent invention to provide a novel arrangement for controlling beamintensity in a digitally-controlled display system.

Another object of the invention is to provide beam intensity controlmeans in a display system, in which beam intensity is controlled byother than the differentiation of deflection voltages.

' A further object of the invention is to provide, in adigitally-controlled display system of the type in which the display isformed by different length strokes written during successive equal clockperiods, beam intensity control to make each stroke be of a uniformintensity.

These and other objects of the present invention are achieved byproviding an arrangement which is supplied with the writing rates ofeach stroke along the X and Y axes. These rates represent the stroke'slength along the two axes. The rates are converted into analog signalsand are supplied to a novel length estimator whose output is an estimateof the stroke's length L. The estimator implements the equation L=k(X/2Y/2 H2) where X and Y represent the strokes writing rates along the Xand Y axes, P is the larger of X or Y and k is either equal to oneresulting in an estimate error of 12 percent, or is equal to 0.94,resulting in an estimate error of :6 percent. The estimated length isused to control the beam's intensity so that strokes of differentlengths have the same intensity.

The novel features of the invention are set forth with particularity inthe appended claims. The invention will best be understood from thefollowing description when read in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is an example of a displayedletter R formed by a succession of strokes;

FIG. 2 is a chart of the writing rates for each of the strokes shown inFIG. 1;

FIG. 3 is a block diagram of a beam intensity control arrangement inaccordance with the teachings of the present invention;

FIG. 4 is a curve useful in explaining the estimate error produced inaccordance with the teachings of the present invention;

FIGS. 5a, 5b, 6, 7a and 7b are diagrams of curves or signals useful inexplaining the operation and purpose of different units, shown in FIG.3;

FIG. 8 is a schematic diagram of the novel part of the arrangement shownin FIG. 3; and

FIG. 9 is a partial schematic diagram of a modification of thearrangement shown in FIG. 8.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention may best bedescribed by first considering the type of system in which the inventionis incorporated. The invention is assumed to be incorporated in adisplay system in which each line or symbol, such as the letter R, shownin FIG. 1, is formed by one or more strokes formed on a display surface12. The surface may be assumed to define a plurality of points 14arranged in a matrix of rows in a vertical direction or axis Y, andcolumns in an X axis. The distance or length between adjacent rows orcolumns represents a unit of length. The symbol, such as R, is formed bydeflecting an unblanked beam during each clock period between selectedpoints to form or write a succession of strokes, designated A-l-l. Inthe present explanation, it is assumed that the maximum stroke lengthalong each axis is not more than 3 units of length.

In practice, for each symbol to be displayed, deflection or writingrates for each stroke may be stored in terms of the strokes length alongeach axis. The information for each stroke is then sequentially read outduring each clock period, during which the stroke is formed. For theparticular example, the information may be as outlined in the chartshown in FIG. 2. Assuming that at a given point in time, the beam is atpoint at which the letter R is to be displayed, the letter may bedisplayed by first forming stroke A, by providing the beam with adeflection rate of 0 units in the X axis, represented by 0X, and +3units of deflection in the Y axis, represented by +3Y. Each of the otherstrokes 8-6 is formed during a successive clock period, while the beamis unblanked. The beam could then be returned from point 14b to point143 during a succeeding clock period during which the beam is blanked,and during the following clock period stroke lO60ll 06l0 H would beformed to complete the display of the letter R.

It should be apparent that since the strokes may be of differentlengths, though each is formed during an equal period, their intensitieswould be inversely proportional to their lengths unless beam intensitycontrol is provided. In accordance with the present invention, this isaccomplished by using the X and Y deflection rates of each stroke, asthe beam is deflected to form r the stroke, to compute an estimate ofthe stroke's length. The estimated strokes length is then used tolinearly control the beams intensity so that all strokes, regardless oflength, are of the same intensity. The invention includes a simple, yethighly novel circuit for stroke length estimating.

The invention is diagrammed in block form in FIG. 3 wherein blocks 22and 24 represent storage units which respectively store the X and Ydeflection rates or simply the X and Y rates for each stroke of aparticular symbol to be displayed. One example of such rates isrepresented in FIG. 2. Assuming that maximum rate in each axis is 3, theX rate in binary representation of a particular stroke is supplied to Xbuffer 26, at the start of the clock period when the stroke is to beformed, while the strokesY rate is loaded in Y buffer 28. The buffersare assumed to be of the parallel input parallel output type.

The invention includes a delay unit 30, which together with units 22 and24 of unit 20 are clocked by a clock pulse in line 31. The function ofthe delay unit 30 is to delay the supply of the clock pulse to thebuffers which when clocked unload their contents in parallel into D/Aconverters 32 temporarily 34. Thus, the function of the buffers is totemporarily hold the X and Y rates during the clock delay periodprovided'by unit 30. The function of this delay unit will be explainedlater. Briefly, it is to compensate for the inherent time delay ofpresent day deflection amplifiers.

The converters 32 and 34 respectively convert the X and Y rates intoanalog signals which are supplied to a novel stroke length approximator35. The latter provides an analog signal which is a close approximationof the length, designated L,.of the particular stroke which is beingformed.

I As is appreciated, L may be expressed in terms of X and Y by L V X Y.To generate theexact value of L, based on the above expression, requiresthe use of logarithmetic amplifiers which are expensive and complex.This requirement is eliminated in the present invention by havingapproximator 35 approximatethe length L by a relatively simplearrangement, with a total error of less than 12 percent. If desired, theerror can be reduced to be not greater than 6 percent. In operation,approximator 35 implements the equation I L=k(S/2 Y/2 P12), where K is aselected constant nand P is either X or Y depending on which is thelargest of the two rates. If a plot of this approximation is made forthe equation V cos+sin 0=1 with 0 varying from 0 to 90, the resultinggraph is as the one shown in FIG. 4. Basically, this graph is generatedby adding Vi cos 0 and 5: sin 0 of either cos 0 or sin 0 which ever isgreater and determining the percent difference of the sum from one (1).It can be seen that the total error is less than 12 percent and isalways greater than the true value. If the sum is multiplied by a kfactor of 0.94, the error never exceeds :6 percent, as represented bythe dashed line 36.

As will be shown hereafter approximator 35 is implemented in a novelmanner to provide the length approximation in accordance with theequation L k (X/2 Y/2 H2).

Thus, the amplitude of the output of approximator 35 is a close estimateof stroke length with an error of not more than 6 percent if k=0.94 andof not more than 12 percent if k=l. This output is supplied to anamplifier driver 40 through a controllable gate 41. Preferably, theoutput of the approximator 35 is adjusted by a pedestal level adjuster42. The function of the latter is to adjust the approximator output sothat the intensity level of the symbols is substantially the same asother elements, such as lines, which are displayed on the displaysurface 12. The driver 40 drives a non-linear video amplifier 43 whoseoutput is supplied to the display unit to control beam intensity such asby controlling the negative voltage in the grid of the display tube.

As is appreciated by those familiar with CRTs, a CRT has a non-lineartransconductance as shown in FIG. 5a wherein the abscissa denotes gridto cathode voltage designated V and the ordinate designates beambrightness. To compensate for this non-linearity, the amplifier 43 ischosen to have a non-linear gain as shown in FIG. 5b. Therein, line 44represents an ideal gain characteristic, while lines 45a-45c representactual gain characteristics of a non-linear amplifier.

Gate 41 is controlled by a leading and trailing edge control unit 45which is assumed to be supplied with a beam unblank/blank signal.Basically, unit 45 consists of two manually adjustable one shots. Theiroperation may best be explained in conjunction with FIG. 6. Assumingthat the unblank/blank signal is a positive signal 46 whose positiveleading edge 47 at t, represents the unblank signal, one of the oneshots is operated to provide a positive signal 48 starting at t, where t-t is adjustable. Thus, positive signal 48 opens gate 41. Likewise, whenthe negative trailing edge 50 of signal 46, representing the blanksignal, is received at 1,, the second one shot is activated to provide anegative signal 51 with a leading edge at t where t t, is adjustable.Signal 51 closes the gate 41. Such an arrange ment provides anadvantageous control for stroke start and end points.

The operation of the system described so far may best be summarized witha specific example which will be explained in conjunction with FIGS. and7b. Let it be assumed that a symbol 60 (FIG. 7a), consisting of twostrokes 61 and 62 is' to be displayed and the required deflectionrates'of the two strokes along one axis such as the X axis are asdesignated by lines 64 and 65. It is also assumed that stroke 61, inaddition to having twice the X deflection rate of stroke 62, is thelonger of the two. Let it be assumed that the beam is at a point 66 andthat at time t, a system clock pulse 67 (FIG. 7b) is applied to unit 20.Unit provides the CRT with X and Y deflection rates for stroke 61. InFIG. 7b, only the X deflection rate represented by line 64 is shown.

As is appreciated, due to the delay in present day deflectionamplifiers, the deflection of the beam from point 66 to end point 67starts at a low rate until the full deflection rate is achieved asrepresented'by line 64a. This delay is designated by t and is accountedfor by delay unit 30. Thus, whereas the unit 20 supplied the X and Yrates to buffers 26 and 28 at t,, they do not change state until theyare clocked by the delayed clock pulse 67d at time At time t, the gate41 is operated by the unblank signal 70 which is provided by unit 20through control unit 45. Consequently, the potential at node 41:: risesfrom a reference potential such as ground to a potential or voltagecontrolled by the pedestal level adjuster 42. This level is representedin FIG. 7b by numeral 71. Then at t,', the buffers are clocked andreceive the X and Y rates for stroke 61. They in turn activate theconverters 32 and 34 whose analog outputs are operated upon byapproximator 35. The latter estimates the length L of stroke 61 andraises the potential at point 41): above the pedestal level 71 by anamount proportional to the length L. This is represented by line 73.Thus, it is seen that while the beam is deflected to form stroke 61 itsintensity is controlled by a potential at point 41x, represented by line75 which is a function of its length.

At time one system clock period after t,, the unit 20 is again clockedto supply the X and Y rates for stroke 62. However, due to the delay t,the beam does not reach the end of point 67 of stroke 61 until t Thus,until t, the intensity of the beam is controlled by the levelrepresented by line 75 which is a function of the length of stroke 61.Then at t, the buffers are again clocked to be set to the X and Y ratesof stroke 62. Since stroke 62 is shorter than stroke 61, theapproximators output is reduced as represented by line 80. Consequently,the voltage at 41x which controls beam intensity is decreased during theformation of stroke 62. The intensity controlling voltage at point 41xfor stroke 62 is represented by line 82.

The unit 20 is again clocked at t, and since the end of the symbol 60was reached its output to the buffers is set to zero. However, due tothe delay t, the beam does not reach the end point 84 of stroke 62 untili when the buffers are loaded with the all zero values. Consequently,the contribution to the potential at 41x is only that of the pedestaladjuster 42, as represented in FIG. 7b by line 71. Thereafter, duringthe next system clock pulse at I the unblank signal 70 is terminated andthe beam is blanked by the closing of gate 41 so that the potential atpoint 41x is again zero. If desired, the unblanking signal 70 may beterminated by unit 20 at t, and control unit 45 may be used to actuallyclose the gate 41 at time t, after t, as represented by dashed line 84.7

From the foregoing description it should thus be appreciated that in thepresent invention, the intensity of the beam as it is deflected to formeach stroke of a symbol is controlled as a function of stroke length.Consequently, the strokes which may be of different lengths, thoughformed during equal duration clock periods, are of substantially uniformintensity.

Reference is now directed to FIG. 8 which is a schematic diagram of oneembodiment of the approximator 35, the gate 41 and the pedestal leveladjuster 42. Basically, the approximator 35 comprises a resistancenetwork which includes equal resistors R1, R2 and R3. Also shown is acapacitor C. One side of the capacitor is grounded and the other isconnected to a point 41x. The output of digilog 32 at which the analogvalue X is applied is connected to point 41:: through R1 and to theanode of a diode D1, while the output of digilog 34, at which the analogvalue Y is applied, is connected to point 41x through R3 and to theanode of diode D2. R2 has one end connected to point 41:: and the otherend to the anode of a diode D3, whose cathode is connected to thecathodes of D1 and D2 at point 92. The anode and cathode of D3 areconnected to positive and negative voltages, such as +l5V and l5Vthrough resistors 74and 75 respectively, so that D3 is always forwardbiased.

The pedestal level adjuster 42 is shown comprising a variable resistor97, connected across a potential of +l5V, and with its movable armconnected to point 41X through a resistor 98. The gate 41 consists of aswitchable transistor Q1, shown for explanatory purposes as being of theNPN type. The emitter of O1 is grounded and the collector is connectedto point 411:. The base is connected to control unit 45 through resistorand through a resistor 101 to a negative potential such as I5V.

In operation, during beam blank periods, O1 is conducting or ON therebyconnecting point 41x or.capacitor C to ground through the transistor'scollector to emitter junction. The pedestal level adjuster 42 is set toprovide the desired pedestal level, designated by nuv metal 71 in FIG.7b, to the driver 40 through an output resistor 102. When the unblankingsignal 48 (See FIG.

6) is applied to the base of Q1 from the control unit 45, O1 is drivento cut off or OFF. Thus, the potential at 41x rises to tee levelcontrolled by the setting of resistor 97. This level is represented byline 71 in FIG. 7b. Then y when the buffers are clocked such as t,, theoutputs of the digilogs 32 and 34 represent the X and Y deflection ratesof the stroke being formed, whose L is approximated by approximator 35.

As'previously pointed out, the approximator 35 estimates L by deriving avalue k (X/2 Y/2 H2). In FIG. 8, k is assumed to be 1. Assuming that XY, the desired estimated value of L is In the circuit shown in FIG. 8,when X Y, i.e., the input from 32 is greater than the input from 34.Consequently, diode D1 becomes forward biased and D2 is backbiased. Thevoltage drop across D1 is compensated by the voltage drop across D3.Consequently, the output of digilog 32 is effectively connected toterminal 41:: through R1 and R2 in parallel which effectively represents54R. However, digilog 34 at which the Y rate is applied is connected toterminal 41x through R3=R. Thus effectively the rise in potential at411: is a function of X+Y/2.

On the other hand when Y X, D2 is forward biased and D1 is backbiased.Thus, the total increase of the potential at 41x is related to Y+Xl2.When X=Y due to l060ll 0612 some difference between the actualproperties of D1 and D2, one of them becomes forward biased and theother is back biased so that the potential increase is related to eitherX+Yl2 or X /2 Y. However, since X=Y, the resultant increase in the same,regardless of which diode is forward biased.

As previously pointed out, in FIG. 8, k is assumed to be 1 in which casethe maximum error is 12 percent. If desired k can be made to equal 0.94for an error of 16 percent by incorporating a variable resistor 95, asshown in FIG. 9, and by setting it so that only 0.94 of.

.the potentialat terminal 41x is applied to the driver 40 withcontrolling beam intensity in a display system, it

can be employed whenever a distance between two points is to becomputed, if the distances between the points along two orthogonal axesare known.

The invention has been described in connection with controlling beamintensity when strokes which together form symbols (such as the letterR) are produced. It should be apparent that if desired a separate lengthapproximator with its associated pedestal level adjuster and gate may beused to control beam intensity when strokes which form parts of lines orother displayed elements are produced. The generated intensity controlsignal from such an arrangement can be supplied to' amplifier driver 40as represented in FIG. 3 by line 108.

Although particular embodiments of the invention have been described andillustrated therein, it is recognized that modifications and variationsmay readily occur to those skilled in the art and consequently it isintended that the claims be interpreted to cover such modifications andequivalents.

WHAT IS CLAIMED l8:

1. in a digitally-controlled display system of the type in which adisplay is formed on a display surface of a display tube containing adeflectable beam whose intensity is controllable by producing asuccession of strokes, each stroke being formed by deflecting theunblanked beam from a selected stroke start point on said surface to aselected stroke end point, each stroke being formed during a fixed clockperiod, with the strokes being of varying lengths, the system furtherincluding data containing means which contain data related to the lengthof each stroke along a first axis and its length along a secondorthogonal axis, an arrangement for controlling the beam intensity as afunction of stroke length, comprising:

first means for utilizing during each clock period the length data alongsaid first and second axes of a stroke to be formed during said clockperiod and for estimating the strokes length between .its start and endpoints, the estimated length definable as L being a function of n x/2 mm).

it is deflected from the strokes start point to its end point.

2. The arrangement as recited in claim 1 wherein 3. The arrangement asrecited in claim 1 wherein k=0.94.

4. The arrangement as recited in claim 1 wherein said data containingmeans contain the strokes length data along said X and Y axes in digitalform and said first means include buffer means for receiving the strokeslength data along each axis from said data containing means and forholding it during the period when said beam is deflected from thestrokes start point to its end point, and said first means furtherinclude converting means for converting said data in said second meansduring said period into related analog signals.

5. The arrangement as recited in claim 4 wherein said first meansinclude estimating means coupled between said converting means and saidsecond means for providing the latter with an input potential which is afunction of the estimated strokelength.

6. The arrangement as recited in claim 4 wherein said converting meansinclude a first converter for providing an analogsignal which is afunction of the strokes length along the X axis and a second converterfor providing an analog signal which is a function of the strokes lengthalong the Yaxis, said first means further including estimating meanscoupled to said first and second converters and further coupled to saidsecond means at a junction point, for providing at said junction point apotential which is a function of the estimated stroke length.

7. The arrangement as recited in claim 6 wherein said estimating meanscomprises first, second and third resistors, said first resistor beingconnected between said first converter and said junction point, saidthird resistor being connected between said junction point and saidsecond converter, said second resistor having one end coupled to saidjunction point, and diode means for coupling the other end of saidsecond resistor to said first and second converters, whereby when theanalog signal from said first converter is greater than the analogsignal from said second converter, said first and second resistors areeffectively in parallel and when the analog signal from said secondconverter is greater than the analog signal from said first convertersaid second and third resistors are effectively in parallel.

8. The arrangement as recited in claim 7 wherein said diode meansinclude first, second and third diodes with their cathodes connectedtogether at a common point, the anodes of said first and second diodesbeing respectively connected to said first and second converters, theanode of said third diode being connected to said other end of saidsecond resistor and means for maintaining said third diode in a forwardbiased state.

9. The arrangement as recited in claim 8 wherein Fl when the potentialat said junction point is directly applied to said second means.

l060ll 0613 first means for receiving 10. The arrangement as recited inclaim 8 further including variable resistive means at said junctionpoint for controlling the percentage of the potential at said junctionpoint which is applied to said second means to thereby control the valueof k to be less than 1.

11. In combination with a display unit of the type which includes a beamwhich is deflectable on a display surface from one point to another toform a stroke therebetween, the unit including means which areresponsive to a beam intensity control signal to control the beamintensity, and a symbol data storage unit which contains the deflectionrates of each stroke of a symbol to be displayed in terms of the strokeslength along two orthogonal axes of said display surface, said axesbeing definable as X and Y, said unit being clockable by a clock pulseof a sequence of clock pulses supplied thereto to supply said displayunit with the stroke's deflection rates in said X and Y axes so as todeflect said beam from the strokes start point to its end point, anarrangement for controlling the intensity of said beam as it isdeflected to form said stroke, the arrangement comprising:

from said storage unit the deflection rates of said stroke along said Xand Y axes and for converting said rates into a potential at an outputjunction of said first means, said potential being a function of k(X/2Y/2 P12), wherein X represents the strokes X deflection rate, Yrepresents the stroke's Y deflectionrate, P is the greater of X or Y andk is a constant; and

second means for utilizing said potential to provide a beam intensitycontrol signal to said display unit, said control signal being afunction of the amplitude of said potential.

12. The arrangement as recited in claim 11 wherein the X and Ydeflection rates from said storage unit are in digital form, said firstmeans include a first buffer for receiving the strokes X deflection ratefrom said storage unit and a second buffer for receiving the strokes Ydeflection rate from said storage unit, first and seconddigital-to-analog converters coupled to said first and second buffersfor converting the digital strokes deflection rates in said buffers intorelated X and Y analog signals, and stroke length estimator means forproviding said potential as a function of said X and Y analog signals.

13. The arrangement as recited in claim 12 further including delay meansresponsive to said clock pulse for providing said first and secondbuffers with a thereto.

delayed activating clock pulse to activate said buffers to receive saidX and Y deflection rates from said and to hold said rates therein untila subactivating clock pulse is applied storage unit sequent delayed 14.The arrangement as recited in claim 12 wherein said stroke lengthestimator means comprises first, second and third resistors, said firstresistor being connected between said first converter and said junctionpoint, said third resistor being connected between said junction pointand said second converter, said second resistor having one end coupledto said junction point, and diode means for coupling the other end ofsaid second resistor to said first and second converter, whereby whenthe analog signal from said first converter is greater than the analosignal from said second converter, said first and secon resistors areeffectively in parallel and when the analog signal from said secondconverter is greater than the analog signal from said first convertersaid second and third resistors are effectively in parallel.

15. The arrangement as re ited in claim 14 wherein said diode meansinclude first, second and third diodes with their cathodes connectedtogether at a common point, the anodes of said first and second diodesbeing respectively connected to said first andsecond converters, theanode of said third diode being connected to said other end of saidsecond resistor and means for I maintaining said third diode in aforward biased state.

16. The arrangement as recited in claim 15 wherein k=l when thepotential at said junction point is directly applied to said secondmeans.

17. The arrangement as recited in claim 15 further including delay meansresponsive to said clock pulse for providing said first and secondbuffers with a delayed activating clock pulse to activate said buffersto receive said X and Y deflection rates from said storage unit and tohold said rates therein until a subsequent delayed activating clockpulse is applied thereto. g p

18. The arrangement as recited in claim 17 wherein k--l when thepotential at said junction point is directly applied to said secondmeans.

19. The arrangement as recited'in claim 17 further including variableresistive means at said junction point for controlling the percentage ofthe potential at said junction point which is applied to said secondmeans to thereby control the value of k to be less than 1.

1. In a digitally-controlled display system of the type in which adisplay is formed on a display surface of a display tube containing adeflectable beam whose intensity is controllable by producing asuccession of strokes, each stroke being formed by deflecting theunblanked beam from a selected stroke start point on said surface to aselected stroke end point, each stroke being formed during a fixed clockperiod, with the strokes being of varying lengths, the system furtherincluding data containing means which contain data related to the lengthof each stroke along a first axis and its length along a secondorthogonal axis, an arrangement for controlling the beam intensity as afunction of stroke length, comprising: first means for utilizing duringeach clock period the length data along said first and second axes of astroke to be formed during said clock period and for estimating thestroke''s length between its start and end points, the estimated lengthdefinable as L being a function of k(X/2 + Y/2 + P/2), wherein Xrepresents the stroke''s length along said first axis, Y represents thestroke''s length along said second axis, P is the greater of X or Y andk is a constant; and second means for utilizing the estimated strokelength for controlling the intensity of said beam as it is deflectedfrom the stroke''s start point to its end point.
 2. The arrangement asrecited in claim 1 wherein k
 1. 3. The arrangement as recited in claim 1wherein k 0.94.
 4. The arrangement as recited in claim 1 wherein saiddata containing means contain the stroke''s length data along said X andY axes in digital form and said first means include buffer means forreceiving the stroke''s length data along each axis from said datacontaining means and for holding it during the period when said beam isdeflected from the stroke''s start point to its end point, and saidfirst means further include converting means for converting said data insaid second means during said period into related analog signals.
 5. Thearrangement as recited in claim 4 wherein said first means includeestimating means coupled between said converting means and said secondmeans for providing the latter with an input potential which is afunction of the estimated stroke length.
 6. The arrangement as recitedin claim 4 wherein said converting means include a first converter forproviding an analog signal which is a function of the stroke''s lengthalong the X axis and a second converter for providing an analog signalwhich is a function of the stroke''s length along the Y axis, said firstmeans further including estimating means coupled to said first andsecond converters and further coupled to said second means at a junctionpoint, for providing at said junction point a potential which is afunction of the estimated stroke length.
 7. The arrangement as recitedin claim 6 wherein said estimating means comprises first, second andthird resistors, said first resistor being connected between saId firstconverter and said junction point, said third resistor being connectedbetween said junction point and said second converter, said secondresistor having one end coupled to said junction point, and diode meansfor coupling the other end of said second resistor to said first andsecond converters, whereby when the analog signal from said firstconverter is greater than the analog signal from said second converter,said first and second resistors are effectively in parallel and when theanalog signal from said second converter is greater than the analogsignal from said first converter said second and third resistors areeffectively in parallel.
 8. The arrangement as recited in claim 7wherein said diode means include first, second and third diodes withtheir cathodes connected together at a common point, the anodes of saidfirst and second diodes being respectively connected to said first andsecond converters, the anode of said third diode being connected to saidother end of said second resistor and means for maintaining said thirddiode in a forward biased state.
 9. The arrangement as recited in claim8 wherein k 1 when the potential at said junction point is directlyapplied to said second means.
 10. The arrangement as recited in claim 8further including variable resistive means at said junction point forcontrolling the percentage of the potential at said junction point whichis applied to said second means to thereby control the value of k to beless than
 1. 11. In combination with a display unit of the type whichincludes a beam which is deflectable on a display surface from one pointto another to form a stroke therebetween, the unit including means whichare responsive to a beam intensity control signal to control the beamintensity, and a symbol data storage unit which contains the deflectionrates of each stroke of a symbol to be displayed in terms of thestroke''s length along two orthogonal axes of said display surface, saidaxes being definable as X and Y, said unit being clockable by a clockpulse of a sequence of clock pulses supplied thereto to supply saiddisplay unit with the stroke''s deflection rates in said X and Y axes soas to deflect said beam from the stroke''s start point to its end point,an arrangement for controlling the intensity of said beam as it isdeflected to form said stroke, the arrangement comprising: first meansfor receiving from said storage unit the deflection rates of said strokealong said X and Y axes and for converting said rates into a potentialat an output junction of said first means, said potential being afunction of k(X/2 + Y/2 + P/2), wherein X represents the stroke''s Xdeflection rate, Y represents the stroke''s Y deflection rate, P is thegreater of X or Y and k is a constant; and second means for utilizingsaid potential to provide a beam intensity control signal to saiddisplay unit, said control signal being a function of the amplitude ofsaid potential.
 12. The arrangement as recited in claim 11 wherein the Xand Y deflection rates from said storage unit are in digital form, saidfirst means include a first buffer for receiving the stroke''s Xdeflection rate from said storage unit and a second buffer for receivingthe stroke''s Y deflection rate from said storage unit, first and seconddigital-to-analog converters coupled to said first and second buffersfor converting the digital stroke''s deflection rates in said buffersinto related X and Y analog signals, and stroke length estimator meansfor providing said potential as a function of said X and Y analogsignals.
 13. The arrangement as recited in claim 12 further includingdelay means responsive to said clock pulse for providing said first andsecond buffers with a delayed activating clOck pulse to activate saidbuffers to receive said X and Y deflection rates from said storage unitand to hold said rates therein until a subsequent delayed activatingclock pulse is applied thereto.
 14. The arrangement as recited in claim12 wherein said stroke length estimator means comprises first, secondand third resistors, said first resistor being connected between saidfirst converter and said junction point, said third resistor beingconnected between said junction point and said second converter, saidsecond resistor having one end coupled to said junction point, and diodemeans for coupling the other end of said second resistor to said firstand second converter, whereby when the analog signal from said firstconverter is greater than the analog signal from said second converter,said first and second resistors are effectively in parallel and when theanalog signal from said second converter is greater than the analogsignal from said first converter said second and third resistors areeffectively in parallel.
 15. The arrangement as recited in claim 14wherein said diode means include first, second and third diodes withtheir cathodes connected together at a common point, the anodes of saidfirst and second diodes being respectively connected to said first andsecond converters, the anode of said third diode being connected to saidother end of said second resistor and means for maintaining said thirddiode in a forward biased state.
 16. The arrangement as recited in claim15 wherein k 1 when the potential at said junction point is directlyapplied to said second means.
 17. The arrangement as recited in claim 15further including delay means responsive to said clock pulse forproviding said first and second buffers with a delayed activating clockpulse to activate said buffers to receive said X and Y deflection ratesfrom said storage unit and to hold said rates therein until a subsequentdelayed activating clock pulse is applied thereto.
 18. The arrangementas recited in claim 17 wherein k 1 when the potential at said junctionpoint is directly applied to said second means.
 19. The arrangement asrecited in claim 17 further including variable resistive means at saidjunction point for controlling the percentage of the potential at saidjunction point which is applied to said second means to thereby controlthe value of k to be less than 1.